Foundry Interface Engineer

• Review and assess Foundry silicon data against SPICE/design goals and compile SPICE to Silicon gap analysis. Drive foundry partners on CIPs to improve foundry process to meet technology entitlement and product goals.
• Work with foundry to identify potential device parameter changes to enable efficient low-voltage operation
• Work closely with circuit designers to determine what device improvements could improve circuit performance and energy efficiency
• Engage with Foundry partners/third-party vendors to manage foundry PDK/DK and design library collaterals
• Guide internal IP/design teams on appropriate usage of technology attributes/offerings in accordance with product requirements (e.g., performance, power, area, and cost).
• Collaborate with internal third-party infrastructure, customization, test-chip, methodology, and packaging and product test engineering teams for seamless execution of product bring-up and productization.
• Work with test engineers to analyze and validate production wafer data
• Contribute to binning strategy to maximize parametric yield

• 10 + years of post-education experience in FAB/Fabless environments, technology definition and bring-up, device/process architecture, and NPI
• Experience with foundry design kit, SPICE, DR/DRC evaluation, SPICE to Si assessment
• Experience with advanced node device physics (e.g. FinFET/GAA), backside power, product design phases
• Experience with product KPIs, DTCO, and parametric, DLY/PLY analysis/gap closure
• Understanding of low power design techniques (e.g., Vmin reduction, power gating, multi-voltage design, chip power, clock network and optimization)
• Understanding of layout effects and impact to circuit design

Preferred

• Master's degree or PhD in Electrical Engineering, Physics, or other related Engineering field with emphasis on semiconductor materials/devices and device physics (not a substitute for professional experience)
• Production test development experience
• Familiar with advanced FinFET technology nodes (3nm and 2nm)
• Familiar with PDK and device models
• Previous work experience at semiconductor foundries
• Familiar with standard cell design and layout

We’re working to build a more inclusive economy where our customers have equal access to opportunity, and we strive to live by these same values in building our workplace. Block is a proud equal opportunity employer. We work hard to evaluate all employees and job applicants consistently, based solely on the core competencies required of the role at hand, and without regard to any legally protected class.

We believe in being fair, and are committed to an inclusive interview experience, including providing reasonable accommodations to disabled applicants throughout the recruitment process. We encourage applicants to share any needed accommodations with their recruiter, who will treat these requests as confidentially as possible. Want to learn more about what we’re doing to build an inclusive workplace? Check out our Inclusion & Diversity page